A processing system including multiple computing nodes is widely used. Each of the computing nodes in the processing system includes a processor core acting as a process execution part for performing arithmetic operations, and a cache memory that is more quickly accessible than a main memory for storing data. The cache memory is placed between the processor core and the main memory, and retains part of data stored in the main memory. Each computing node performs cache coherency control to maintain data consistency stored in each cache memory (e.g. cache coherency).
For instance, in a multiprocessor system including multiple main memories and multiple processors each containing cache memory, a method for performing cache coherency control is proposed by referring to tag information of the main memory (see Patent Document 1, for example). The tag information of the main memory is information indicating, for each data group corresponding to a cache line, if a dirty cache line exists in a processor other than a processor corresponding to the main memory, and is stored in a tag memory provided in each main memory. The “dirty” is a state of the cache memory whose data is updated but the data in the main memory has not been updated. For example, when data in the main memory, corresponding to certain tag information whose state is dirty, is to be read, a write-back operation to write a dirty cache line to the main memory is performed, and correct data is sent to a request source processer after completing the write-back operation.
Further, in a multiprocessor system including multiple processors sharing a main memory, a cache coherency control method is proposed to read correct data even when a read request is targeted to data in which a write-back operation is being performed (see Patent Document 2, for example). In such a cache coherency control method, when a read request targeted to data in which a write-back operation is being performed is issued, on receiving a completion notice from a main memory indicating that the write-back operation is completed, a read request is again issued to the main memory.
The following is a reference document:    [Patent Document 1] Japanese Laid-Open Patent Publication No. 8-185359,    [Patent Document 2] Japanese Laid-Open Patent Publication No. 10-161930.